This invention relates to MOS (metal oxide semiconductor) decoder device used for synchronous MOS memory devices or the like.
As a decoder device for a synchronous MOS memory device which operates in synchronism to a clock signal, one having a construction as shown in FIG. 1 is well-known in the art. This decoder circuit serves to decode an address signal consisting of address bits A.sub.0 to A.sub.n according to two clock signals CE.sub.1 and CE.sub.1, which are 180 degrees out of phase with each other, thereby selecting a word line WL. If the clock signal CE.sub.1 is at "1" level and the clock signal CE.sub.1 is at "0" level, N channel MOS transistors T.sub.3 and T.sub.7 are turned on so that the potential on a node N.sub.1 and a word line WL is at "0" level. After an address signal consisting of address bits A.sub.0, A.sub.1, . . . , A.sub.n is coupled to P channel transistors T.sub.1-0, T.sub.1-1, . . . , T.sub.1-n, the clock signal CE.sub.1 is inverted to " 0" level to turn a P channel MOS transistor T.sub.2 on and turn the N channel MOS transistor T.sub.3 off.
If the address bits A.sub.0 to A.sub.n are all at "0" level, the node N.sub.1 is held at "0" level. On the other hand, if at least one of the address bits A.sub.0 to A.sub.n is at "1" level, the potential on the node N.sub.1 is changed to "1" level. When the node N.sub.1 is at "0" level, a P channel MOS transistor T.sub.5 is turned on so that the word line WL is brought to "1" level and thus selected. On the other hand, if the node N.sub.1 is at "1" level, an N channel MOS transistor T.sub.4 is turned on so that the word line WL remains at "0" level and is thus not selected.
As is seen from the above, the prior-art decoder circuit of FIG. 1 requires two clock signals 180 degrees out of phase with each other. Besides, there is a certain limitation imposed upon the timing of the generation of pulses, and the clock pulse CE.sub.1 must be inverted from "0" level to "1" level after the inversion of the preceding clock pulse CE.sub.1 from "1" level to "0" level. Unless this timing relation between the two clock pulse signals is met, a malfunction such as simultaneous selection of a plurality of word lines is likely to result. This requirement for the clock signals complicates the circuit and imposes restrictions upon the operating speed, thereby creating various problems.